1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device.
2. Description of the Related Art
In recent years, semiconductor integrated circuit devices have been large-scale integrated, so that it has been important to distribute a clock to each of functional blocks and so forth, which form a semiconductor integrated circuit, by an appropriate delay time.
FIG. 7 shows an example of a conventional semiconductor integrated circuit device, which distributes a clock to each of functional blocks so that delay times are equal to each other. In FIG. 7, functional blocks 61i including load circuits 76i (i=a, b, c, d) are arranged by means of a circuit simulator so that a tree structure is formed and delay times are equal to each other at the terminal nodes (leafs) of the respective functional blocks. In order to amplify weakened clock signals f, buffers 71, 72, 73a, 73b, 74a through 74d, 75a through 75d, and 76a through 76d are provided at the respective nodes.
Also as shown in FIG. 8, a short-circuit is established between the terminal nodes of the respective functional blocks 61i (i=a, b, c, d) in the conventional semiconductor integrated circuit device shown in FIG. 7 to reduce the phase differences between the clock signals at the terminal nodes of the respective functional blocks 61i.
However, in the aforementioned conventional semiconductor integrated circuit device, there is a problem in that the phase differences between the clock signals occur at the input ends of the respective functional blocks due to the variation in manufacturing process and so forth even if delay times are suitably distributed when the device is designed. Although the circuit simulation may be performed in the design stage in view of the phase differences caused by the variation in manufacturing process and so forth, it takes very much time, so that this is not efficient.